A Survey on Efficient Low Power Asynchronous Pipeline Design Based on the Data Path Logic

This paper presents a survey on high-throughput and ultra low-power asynchronous pipeline design method targeting to latchfree and extremely fine-grain design. Since they are asynchronous, these pipelines avoid problems related to high-speed clock distribution, such as clock power, clock skew, and rigidity in handling varied environments. The pipeline communication is structured in such a way that the critical events can be detected and exploited earlier. The survey is mainly done on the data path logic. The data path may be single-rail, dual-rail or combination of the both logic. Asynchronous pipeline based on constructed critical datapath (APCDP) is combination of both the data path. Critical path compose of dualrail logic and noncritical enables singlerail logic. Based on this critical data path, the handshake circuits are simplified, which offers the pipeline low power consumption as well as high throughput by reducing the overhead problems. This design is going to be implemented by SPICE simulations model.